- High Speed Switching Networks
- QoS Algorithms in Broadband Networks
- Internet Security
- Wireless Networks
- Information Theory
- Supervised the Implementation of SDI video Encryption & Decryption Functionalities, 2010-2012.
- Supervised the Implementation of STM4 based FPGA System with Encryption & Decryption Functionalities running at 2.4 Gb/sec, 2008-2010.
- Supervised the Design and Implementation of IDS System, 2008-2009.
- Supervised the Implementation of IPSec FPGA based Chips with Encryption & Decryption Functionalities running at 2.4 Gb/sec, 2005-2006. This chip includes several different Encryption and Decryption standard Algorithms.
Main Architect and Supervisor of the Implementation of FPGA based Chips and IP cores for Router 2003-2004. Functions include:
- Policing Algorithms
- Buffer Management
- Congestion control and avoidance ( EPD, PPD)
- Lookup tables
- Packet Modification
- Segmentation and Reassembly
- Longest Prefix matching
- Functions support ATM, TCP/IP and MPLS protocols
Key Architect of “XeC Switching Chip; Erlang Technology, 2001-2002.
- An 80 Gb/s per Chip, Multi-Channel, Shared Buffer
- This is a switch core chip capable of supporting up to 560Gb/s system
- Supports multicasting and multi-channeling capabilities
Main Architect of “SeC Switching Chip”, a 10 Gb/s per Chip, Multi-Channel, Shared Buffer; Erlang Technology, 1999-2001.
- This is a patented switch core chip capable of supporting a 40Gb/s system, using 4 chips in parallel.
- Also using multi-channel capabilities.
- It supports any port combinations of 622Mb/s, 2.4 Gb/s and 10Gb/s rate.
- It also supports multicasting.
Key Architect of “NPS, Network Processing Chipset”; Erlang Technology, 2000-2001. Supports:
- Scheduling Algorithm for up to 64 k Connections
- Implements proprietary and patented algorithm for WFQ with granularity of up to 2 Kb/s
- Multiple Priority
- Proprietary algorithm for Traffic Shaping with up to 8K flows
- Policing Algorithms
- Buffer Management and congestion control and avoidance
Key Architect of “ALQS, ATM Layer and Quality of Service Chip”; MinMax Technology, 1998.
- Supports distributed Real-time Adaptive Bandwidth Allocation (RABA) among different Ports and Priorities
Main Architect of “WUMCS Switching Chip”, Washington University, 1994-1995.
- 2.4 Gb/s per Chip, Multi-Channel, Shared Buffer
- This is a patented switch core chip capable of supporting 10Gb/s system, using 4 chips in parallel.
- Also uses multi-channel capabilities
- Supports any port combinations of 622Mb/s and 2.4 Gb/s rate.
- Supports multicasting.